wire-efficient multicore architecture VLSI design System Design

The Raw project's approach to achieving these goals is to implement a simple, highly parallel VLSI architecture, and to fully expose the low-level details of the hardware architecture to the compiler so that the compiler or the software can determine, and implement, the best allocation of resources for each application. Raw is a tiled multicore architecture. It is composed of a set of interconnected tiles, each tile comprising instruction, switch-instruction, and data memory, an ALU, FPU, registers, a dynamic router, and a programmable switch.

Graduated level